1. Field of the Invention
The present invention relates to a semiconductor storage device, and more specifically, to a DRAM (Dynamic Random Access Memory).
2. Description of Related Art
A DRAM includes complementary bit lines arranged in perpendicular to word lines, and memory cells arranged in intersections of the word lines and the complementary bit lines in matrix form.
FIG. 6 shows one example of a circuit configuration of a DRAM according to a related art. As shown in FIG. 6, a related memory 600 includes a word decoder 601 and a memory cell array 602. The word decoder 601 includes a word driver 610 driving a word line for selecting any memory cell. The memory cell array 602 includes memory cells 621, 622, and 623 connected to the word driver 610.
The word driver 610 includes inverters In611, In612, and In613 driven by a high-potential side word line driving voltage VPP and a ground voltage GND.
As shown in FIG. 7, each of the inverters In611, In612, and In613 includes a PMOS transistor P1 and an NMOS transistor N1 connected in series between the high-potential side word line driving voltage VPP and the ground voltage GND. Then a control signal CTRL is input to gates of the PMOS transistor P1 and the NMOS transistor N1. A drain of the PMOS transistor P1 and a drain of the NMOS transistor N1 are connected to each other, and each of the word lines WL1, WL2, and WL3 is connected to the node. For example, in writing or reading information according to the control signal CTRL, the inverter In611 of the word driver 610 outputs the high-potential side word line driving voltage VPP to the word line WL1. On the other hand, in holding the information, the inverter In611 of the word driver 610 outputs the ground voltage GND to the word line WL1. The high-potential side word line driving voltage VPP is higher than a power supply voltage VDD. The inverters In612 and In613 also have the same configuration as that of the inverter In611.
The memory cells 621, 622, and 623 include NMOS gate transistors Tr1, Tr2, and Tr3 and capacitors C1, C2, and C3, respectively. For example, a gate of the gate transistor Tr1 is connected to the word line WL1, and one of a drain and a source is connected to a bit line BLT. The other of the drain and the source of the gate transistor Tr1 is connected to a reference voltage HVDD (VDD/2) through the capacitor C1. The memory cells 622 and 623 also have the same configuration as that of the memory cell 621.
Back gates of the gate transistors Tr1, Tr2, and Tr3, which are wells in which the NMOS transistors are formed, are connected to a back gate voltage source 670. Note that an output voltage VBB (hereinafter referred to as VBB) of the back gate voltage source 670 is set to a negative voltage which is lower than the ground voltage GND. This is because it is possible to suppress an individual difference of a transistor threshold value due to the process variation in the DRAM or to enlarge a depletion layer between an n region of the drain or source and a p region of the well of the gate transistor so as to decrease the parasitic capacity between the p region and the n region by setting VBB to the negative voltage. Accordingly, it is generally appreciated and is almost regarded as common knowledge that VBB is set to the negative voltage which is lower than the ground voltage GND in a circuit configuration of a memory such as the DRAM.
The memory cell 621 sets the gate transistor Tr1 to a conduction state based on the voltage of the word line WL1 so as to write/read out information. Otherwise, the memory cell 621 sets the gate transistor Tr1 to a non-conduction state so as to hold charge stored in the capacitor C1. Further, the bit line BLT is connected to a sense amplifier 630. The bit line BLT is connected to the capacitor C1 when the gate transistor Tr1 is in the conduction state, and the charge information of the capacitor C1 is input to the sense amplifier 630 through the bit line BLT. The memory cells 622 and 623 also have the same configuration as well.
In a recent semiconductor storage device such as the DRAM, the manufacturing process has been miniaturized. There is a problem caused by the miniaturization of the manufacturing process that an off-state leak current of the transistor forming the DRAM increases. As the off-state leak current increases, the charge held in the capacitor of the memory cell readily decreases. Therefore, it is needed to frequently perform refresh operation on the DRAM which needs the refresh operation for holding the stored information. Accordingly, there is a problem that the power consumption of the DRAM increases. In order to solve this problem, a negative word line method has been used for the purpose of suppressing the leak current of the memory cell. In the negative word line method, the potential of the word line corresponding to the non-selected memory cell is set to the negative voltage VKK which is lower than the ground potential GND.
FIG. 8 shows one example of a circuit configuration of the negative word line method in which the voltage of the word line corresponding to the non-selected memory cell is set to the negative voltage VKK. As will be seen from FIG. 8, an output voltage of a low-potential side word line driving voltage source 860 (hereinafter referred to as VKK) is employed as a low-voltage side power supply voltage of the inverter included in the word driver 610. Therefore, the potential of the word line in a memory cell non-selection state is the negative voltage VKK which is lower than the ground potential GND. On the other hand, the driving voltage VPP is employed as the potential of the word line in a memory cell selection state. Japanese Unexamined Patent Application Publication Nos. 2005-135461 (related art (1)) and 11-031384 (related art (2)) disclose a technique of applying the negative voltage VBB to the back gate of the gate transistor of the memory cell and applying the negative voltage VKK to the non-selected word line.
However, in order to perform writing to/reading from the memory cells 621, 622, and 623, the logic level of the word lines (WL1, WL2, WL3) alternately repeats H level (VPP) and L level (VKK) at a certain cycle. This means that charging and discharging are repeated at a certain cycle in each word line. Accordingly, the low-potential side word line driving voltage source 860 needs to repeatedly execute absorption of the charge stored in the word line and supplying the negative voltage VKK to the plurality of inverters forming the word driver 610 for each cycle. It is needed to enhance the ability of the low-potential side word line driving voltage source 860. If the enhancement is insufficient, the output of the negative voltage of the low-potential side word line driving voltage source 860 gradually increases in a direction of the positive voltage and becomes unstable as shown in FIG. 9. The low-potential side word line driving voltage source 860 is connected to all the word lines corresponding to the non-selected memory cells as shown in FIG. 8. Therefore, the unstable voltage shown in FIG. 9 is transmitted to all the word lines corresponding to the non-selected memory cells, which makes it impossible to control the off-state leak current of the gate transistor.
As will be seen from the configuration of the gate transistor shown in FIG. 10, each word line is capacity-coupled with a well of the gate transistor of the memory cell through a gate capacitor Cg. In other words, the gate and the well of the gate transistor of the large number of non-selected memory cells in the DRAM chip, which are the low-potential side word line driving voltage source 860 and the back gate voltage source 670, are capacity-coupled through the gate capacitor Cg. Therefore, the unstable voltage output from the low-potential side word line driving voltage source 860 shown in FIG. 9 is transmitted to the back gate voltage source 670 as a noise. Due to the influence of this noise, the voltage VBB output from the back gate voltage source 670 increases or decreases from a predetermined voltage. Further, the potential of the cell node is also suffered from an adverse effect. More specifically, if the writing operation is performed on the memory cell in a state where VBB increases and the reading operation or the refresh operation is performed on the memory cell in a state where VBB decreases, the charge amount decreases compared with a case in which VBB is in the stable condition with a predetermined voltage value. Accordingly, the memory cell stated above results in hold defect. Furthermore, it is extremely difficult to reproduce the above worst condition and to reject the memory cell as a defective cell in a separating process or the like.
In order to overcome this problem, it may be effective to increase response speed of the low-potential side word line driving voltage source 860 or a volume of stabilizing capacitance for removing ripple. However, in order to increase the response speed of the low-potential side word line driving voltage source 860, the response of a voltage determination circuit of a negative charge pump 861 generating the negative voltage needs to be increased, which increases the power consumption of the amplifier in the determination circuit. Further, in order to increase the volume of stabilizing capacitance for removing the ripple, an area of a decoupling capacitor needs to be increased. Therefore, the power consumption or the area of the DRAM chip increases, which causes an adverse effect.
As stated above, according to the related semiconductor storage device, the output of the driving voltage source driving the word lines to the non-selected memory cells can be unstable.